02-09-2015 | Lattice | Design & Manufacture
Lattice Semiconductor has announced availability of the ECP5 Versa development kit to accelerate prototyping and testing of connectivity designs targeted for small cells, microserver, broadband access, and industrial video applications worldwide. The family’s low power consumption, small form factor and low cost make it an ideal connectivity solution and enables design engineers to rapidly add features and functions that complement those delivered by ASICs and ASSPs, reducing development risk and accelerating time-to-market.
To help users interested in the ECP5 device family to quickly design and test application prototypes, Lattice has released an ECP5 Versa development kit. The kit lets customers evaluate the connectivity performance of the ECP5 FPGA with a range of standards, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES. Lattice also offers several proof-of-concept demos with the ECP5 Versa development kit that can help customers accelerate prototyping and testing of their designs.
Additionally, the ECP5 Versa development kit includes the Lattice Diamond Design Software that offers a complete suite of FPGA design tools with an easy-to-use interface, efficient design flow, superior design exploration and more. The Lattice Diamond software suite tailored specifically for the ECP5 Versa kit will be available free of charge to all users purchasing the board, says the company.
“When we developed the ECP5 family, we broke all the rules of conventional FPGA approaches in order to deliver the optimum connectivity solution tailored to meet the demands of compact, low power, high volume communications and industrial applications,” said Deepak Boppana, director, product marketing at Lattice Semiconductor. “ECP5 devices have proven to be an ideal companion chip for ASICs and ASSPs and we believe that the new ECP5 Versa development board will only help to further increase broad adoption across our served markets.”
Lattice optimized the ECP5 family’s architecture with the goal of delivering the best value below 100K LUTs, while adding key new features such as support for soft error correction, and small form factor packages across all densities. Achieving 40% lower cost than competing solutions, optimizations include small LUT4 based logic slices with enhanced routing architecture, dual-channel SERDES to save silicon real estate, and enhanced DSP blocks for up to 4x resource improvements.
