New tools makes it easy to debug designs combining MIPS and ARM CPUs

Imagination Technologies and Lauterbach are jointly making it easy to use Lauterbach's popular TRACE32 tools to debug MIPS heterogeneous CPU based systems or systems that combine MIPS CPUs with ARM CPUs. Lauterbach's TRACE32 is a set of modular microprocessor development tools that provides integrated debug environments for embedded designs. TRACE32 now supports MIPS Release 6 CPUs including the new M-class M6250, the first embedded-class MIPS CPU to incorporate the MIPS On-Chip Instrumentation (MIPS OCI) flexible on-chip CPU debug architecture. Companies can use MIPS OCI to ensure the lowest possible risk and impact on their debug process for highly-integrated heterogeneous SoCs. Norbert Weiss, international sales and marketing manager, Lauterbach, said: "For many years, Lauterbach has supported the popular MIPS architectures and cores. With TRACE32R, the developers who are creating products around MIPS have access to a full range of debug functionality, from bootstrap code to interrupt routines and drivers. Now developers can even use TRACE32 for designs which combine the MIPS and ARM architectures." Jim Nicholas, vice president of MIPS business operations, Imagination, added: "Because so many of our customers use Lauterbach tools, it's important that TRACE32 work with MIPS OCI. This new development continues to extend the MIPS ecosystem, offering designers an even wider choice of leading development tools. The great amount of focus we are putting on continued development of the MIPS roadmap and ecosystem is enabling potential customers to consider using MIPS CPUs in their systems either as a supporting controller or to replace an ARM or other CPU in their SoC. We've had several customers request the multi-architecture debug solution." TRACE32 enables simultaneous debug of the multiple CPUs in a design with 'mixed mode' trace streams. Users can view the interleaved results in a single trace window, with a system-level timestamp to help align the streams. Extended trigger logic enables cross-triggering between the CPU trace logic to make it even easier to debug processor interdependencies, says the company.