Full-flow digital RTL-to-signoff solution cuts development time in half

Cadence Design Systems has announced that Tezzaron Semiconductor has adopted its full-flow digital register-transfer level (RTL)-to-signoff solution for its networking and supercomputing system on chips (SoCs), cutting its development schedules in half. Tezzaron, best known for 3D-ICs and advanced memory devices, has incorporated Cadence tools in its design work from the very beginning. Over the years, Tezzaron’s products have increased in size, sophistication and complexity, prompting the adoption of the full-flow solution. “Our high-performance 3D SoCs really push the limits,” said Anita Rao, VP of engineering, Tezzaron. “High bandwidth, low power, extreme performance - the Cadence flow gives us the tools we need to create these designs quickly and accurately. We have seen huge gains in productivity.” Chip designers strive for low power, high performance and small area - collectively known as ‘PPA’. 3D-ICs typically demonstrate increased performance in a smaller footprint and their short vertical interconnects dramatically reduce power usage. However, optimizing these advantages in a 3D design presents a profoundly complex set of challenges. Cadence addresses these challenges with unified engines and a common data model across the solution, providing best-in-class PPA. The massively parallel architecture and computation allow speedy completion of high-quality SoCs. For implementation, Tezzaron uses the Cadence Genus Synthesis Solution and Innovus Implementation System. This part of the flow incorporates key technologies such as GigaPlace solver-based placement technology, GigaOpt low-power optimization, and CCOpt concurrent clock and datapath optimization. Tezzaron has seen marked improvement in both runtime speed and PPA. For signoff, Tezzaron uses the Tempus Timing Signoff Solution, the Voltus IC Power Integrity Solution and the Quantus QRC Extraction Solution. These tools employ a system of physically aware timing and power optimization capabilities that significantly shorten time to signoff. Tezzaron reports faster runtimes for single- and multi-corner extraction and best-in-class timing and power signoff accuracy, with engineering change order (ECO) iterations reduced by an order of magnitude. “Tezzaron has experienced very positive results,” added Rao. “We are meeting our design specs with fewer ECO loops and faster turnaround time. It’s all about delivering top-quality SoCs while reducing overall time to tapeout. Going with the Cadence full-flow digital RTL-to-signoff solution was the logical choice for our networking and supercomputing SoCs.”