Collaboration accelerates data centre design success with AI-driven flows

07-09-2023 | Cadence | Test & Measurement

Cadence Design Systems, Inc. has expanded its collaboration with Arm to speed data centre silicon success on the Arm Neoverse V2 platform. Through the collaboration, the company has fine-tuned its AI-driven RTL-to-GDS digital flow for Neoverse V2 and produced corresponding 5nm and 3nm RAKs, empowering customers to achieve PPA targets faster. In addition, the Cadence AI-driven verification full flow supports Neoverse V2, providing designers with optimal verification throughput and preparedness for Arm SystemReady compliance.

Cadence AI-Driven Digital Full Flow for the Neoverse V2 Platform

The comprehensive AI-driven Cadence RTL-to-GDS digital full flow RAKs for 3nm and 5nm nodes includes the Genus Synthesis Solution, Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking, Conformal Low Power, and the AI-based Cadence Cerebrus Intelligent Chip Explorer.

The digital RAKs supply Arm Neoverse V2 designers with many key benefits. For example, the Cadence Cerebrus AI capabilities automate and scale digital chip design, providing better PPA and improving designer productivity. Cadence iSpatial technology offers an integrated, predictable implementation flow for faster design closure. The RAKs comprise a smart hierarchy flow that supplies optimal turnaround times on large, high-performance CPUs. The Tempus ECO technology provides signoff-accurate final design closure based on path-based analysis. Finally, the RAKs include the GigaOpt activity-aware power optimisation engine to lower dynamic power consumption greatly.

The Cadence AI-driven verification full flow optimised to support Arm Neoverse V2 includes the Xcelium Logic Simulation Platform, Palladium Enterprise Emulation Platforms, Protium Enterprise Prototyping Systems, Helium Virtual and Hybrid Studio, Jasper Formal Verification Platform, Verisium Manager Planning and Coverage Closure tools, Perspec System Verifier, and VIP and System VIP tools and content for Arm-based designs.

The verification full flow provides Neoverse V2 designers with pre-silicon SBSA compliance verification and optimised PCIe integration. In addition, the Cadence Helium Virtual and Hybrid Studio incorporate editable virtual and hybrid platform reference designs for Neoverse V2, including Arm Fast Models, to jumpstart early software development and verification. The Helium gearshift technology allows customers to position workloads in a high-performance hybrid environment before shifting to a fully accurate RTL environment, providing detailed verification using either the Palladium or Protium platforms.

"The growing demand for complex workloads such as big data analytics, HPC and ML inference requires specialised compute solutions that achieve greater performance and efficiency," said Eddie Ramirez, vice president of go-to-market, Infrastructure Line of Business at Arm. "Through this latest collaboration, customers can leverage Cadence's comprehensive digital and verification flows to validate their solutions and bring the power of their Neoverse V2-based products to market faster. Furthermore, silicon partners will benefit from these advanced design flows when running their EDA workloads on Arm-enabled servers and cloud instances."

"Customers are always looking to accelerate the pace of innovation, and the Arm Neoverse V2 platform provides the foundation needed to address advanced compute requirements for data center silicon success," said Kam Kittrell, vice president, product management in the Digital and Signoff Group at Cadence. "Through our expanded collaboration with Arm, customers using the AI-driven digital full flow 3nm and 5nm RAKs for Neoverse V2 designs benefit from improved productivity and faster time to tapeout. In addition, by optimising our AI-driven verification full flow, customers have access to all the tools necessary to verify RTL and perform pre-silicon software validation to ensure full system success."

The digital and verification flows support the Cadence Intelligent System Design strategy, allowing customers to achieve SoC design excellence.

By Seb Springall