Advanced modelling process for AI chip designs announced

Sondrel has announced an Advanced Modelling Process for AI chip designs. This runs through every stage of a chip's design to 'prove' that the design is what was specified – Functional Verification – and does what it is supposed to do – Performance Verification.

Paul Martin, Sondrel's global field engineering director, explained, "AI chips are extremely complex to design because of the huge amounts of data that must flow around them between the heterogeneous processors, IO and the memory. There cannot be periods when the processors are stalled waiting for data, which is more complicated when the chip has several different types of processors, each with different data traffic requirements. This new process enables us to analyse and balance the dataflow through the chip whilst executing the software workloads on the AI chip.

"This uses accurate, cycle-based, system performance modelling early in the design cycle in advance of RTL development, enabling us to check that the design will meet its specification. The process then continually evolves as RTL and eventually silicon becomes available to validate the design performs as specified. To accelerate the design process, we base the design on our Architecting the Future platform to ensure that we have a reliable, predictable path to market. This means we are reusing pre-verified design elements in the process that constrain the solution space whilst ensuring high confidence in the integration of those elements, which also reduces risk and time to market."

Power consumption by AI is a hot topic, with some predictions saying that the power consumption of data centres could triple the world's energy needs. With AI proliferating everywhere to make devices smarter, there is an evident drive to process data as much as possible before sending it to the cloud – so-called 'AI at the Edge'. To do this efficiently means that the power consumption of these compute-intensive chips must be minimised, which means using advanced nodes to hit the targets. The company has always specialised in designing at the leading edge of chip technology and is currently working on 3nm designs. Advanced process technologies allow power usage to be constrained while delivering the performance from using billions of transistors needed from these ultra-complex custom chips.

A key to the process is that it can extract the behavioural interaction between the processors and the memory and then map it onto the rest of the chip's functions. This insight enables the company's designers to see how the chip performs and optimise the design to achieve the required balance of power, performance, and area.