3D stacking technology will beat the bandwidth bottlenecks
10-11-2015 | By Paul Whytock
What are seen as the first heterogeneous SiP devices that integrate HBM2 DRAM with FPGAs have been developed by US semiconductor company Altera.
The company believes these Stratix 10 DRAM System-in-Package (SiP) devices will offer over 10X higher memory bandwidth by combining FPGAs and high-bandwidth memory die into a single package. This amount of bandwidth is needed in data centre, broadcast and high-performance computing systems.
The heterogeneous SiP devices combine stacked High-Bandwidth Memory (HBM2) from SK Hynix with high-performance Stratix 10 FPGAs and the devices are enabled using Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology.
SK Hynix’s HBM2 provides high bandwidth while using less power in a small form factor. It vertically stacks DRAM die and interconnects them using through-silicon vias and micro bumps. Integrating the HBM2 in a heterogeneous SiP implementation enables Altera to package the DRAM memory closely to the FPGA die.
Intel's EMIB technology uses a small high-performance, high-density silicon bridge to connect multiple die together in a single package. EMIB has very short traces between die which facilitates higher performance and higher throughput at lower power compared to interposer-based solutions.
The heterogeneous SiP strategy is to integrate into a single package a monolithic FPGA with advanced components, such as memory, processors, analog, optical and various hardened protocols.
Designers can start Stratix 10 projects today using Fast Forward Compile performance evaluation tools and Altera says it will start shipping Stratix 10 FPGAs and SoCs in 2016 and Stratix 10 DRAM SiP products will start shipping in 2017.
