InGaAs channels can cut vertical NAND costs
08-12-2015 | By Paul Whytock
The integration of high mobility InGaAs as a channel material for 3D vertical NAND memory devices formed in the holes with the diameter down to 45nm has been demonstrated for the first time by electronics research centre Imec.
The development of this type of channel material is important because it enhances transconductance and read current. Being able to facilitate this means that further cuts in vertical NAND costs can be achieved by adding additional layers in 3D vertical architecture.
To overcome any scaling issues in conventional planar NAND flash memory technology that can be disrupted by serious cell-to-cell interferences and read noise due to aggressively scaled dimensions, non-volatile 3D NAND flash memory technology is employed.
However, existing 3D NAND devices with a poly-Si channel typically have a drive current that will linearly decrease relative to the number of memory layers. This is not sustainable for long-term scaling because the conduction in the poly-silicon channel material is governed by grain size distribution and handicapped by scattering at the grain boundaries and charged defects.
To boost the drive current in the channel, Imec replaced the poly-Si channel material with InGaAs through a gate first-channel last approach.
The channel was formed by metal organic vapor phase epitaxy showing good III-V growth selectivity to silicon and hole filling properties down to 45nm.
According to the research centre the resulting III-V devices proved to outperform the poly-Si devices in terms of on-state current and transconductance without degrading memory characteristics such as programming, erase and endurance.
Imec’s research into advanced memory is conducted in cooperation with key partners in its CMOS programs. These include; Samsung, Micron-Intel, Toshiba-Sandisk, SK Hynix, TSMC and GlobalFoundries.
