Renesas Will use RISC-V Cores in their ASSPs

Recently, Renesas announced that they would use RISC-V cores in their Application Specific Standard Products. What is RISC-V, what are ASSPs, and could RISC-V become more popular than ARM?

What are ASSPs?

The term ASSP stands for Application Specific Standard Product and must not be confused with ASIC. While both ASICs (Application Specific Integrated Circuit), and ASSPs are virtually identical in design and construction, ASSPs perform a specific function and designed to be used in a wide range of applications. In contrast, ASICs perform a specific function and used in a specific application. An example of an ASSP would be a USB controller, op-amp, or a logic chip whereas an example of an ASIC would b a bitcoin miner which is only used in bitcoin mining rigs. 

What is RISC-V?

RISC-V, which is pronounced RISK 5, stands for Reduced Instruction Set Computer and is an open-source ISA that describes the instructions and bit construction for a CPU. While the fundamental construction of a RISC-V CPU can vary, the result must be the same, as is with x86 processors (AMD and Intel have completely different silicon, but they both perform the same function).

Unlike Complex Instruction Set Computers (CISCs), RISC focuses on having simpler, fewer instructions which not only reduce the complexity of the resulting CPU, but allows for lower power operation as well as more silicon space to fit either advanced co-processors, signal processors, peripherals, and even additional cores. Many SoCs that power single board computers such as the Raspberry Pi are based on RISC CPUs (such as ARM), which integrate the CPU, GPU, and MMU in a single package.

RISC-V was first introduced in 2010 and was designed to be an open-source ISA that could be used by research institutions, developers, engineers, and businesses. Currently, the RISC-V architecture describes 32, 64, and 128-bit processors, uses little-endian, and page sizes of 4KiB while integrating 16 or 32 general-purpose registers with one register always reading 0. Interestingly, the use of a zero register demonstrates how a RISC system minimises the number of instructions; a zero register allows for moving one register into another register using an ADD to register 0 then stores in the target register instead of needing a dedicated MOV (or LD) instruction.

Renesas Announces they will use RISC-V in future ASSPs

Recently, Renesas announced that they will use RISC-V processors in their ASSPs. According to Renesas, the move to use RISC-V will open up opportunities thanks to the use of open-source designs and will help to avoid paying royalties for using processors such as ARM. The use of RISC-V CPUs will also allow for the easy development of software platforms that will allow customers to apply programmable parameters to standard parts, and this will create products that can be optimized for their application. Renesas has also stated that the use of RISC-V eliminates investment barriers thanks to RISC-V being freely available. It is hoped that samples of the new product lines will be available by 2021, and the RISC-V cores are being provided by Andes Technology who develop both RISC-V cores and software development environments for RISC-V products.

Will RISC-V become more popular than ARM?

One of the biggest advantages of RISC-V over ARM is the lack of royalties; companies that use ARM technology in their products (mainly those who develop microcontrollers and processors with ARM cores), have to pay royalties. Since RISC-V is open source, it is freely available for anyone to utilise in either a prototype or full-fledge commercial product. 

RISC-V also carries the advantage that it is open-source, and thus is more likely that bugs and errors are recognised and resolved. ARM, however, is entirely developed internally, and as such bugs may not be patched for long periods of time. This also makes it hard to identify potential bugs in the system as only those who work at ARM can view the source and designs. 

Open-source designs such as RISC-V also have the opportunity to establish industry standards, and potentially forming a unified instruction set that allows for hardware to more easily talk at the machine code level. Many companies develop their own designs and platforms, thinking that they will define how the industry should work. However, more times than not, unified standards, such as protocols and file systems, are defined by an industrial action group consisting of many companies who all want their products to work with each other. As was the case in the ISA bus (industry standard architecture bus), CPU design may see itself shift towards an open-source design that requires no royalties, any member can introduce improvements. Errors can be quickly spotted and fixed.

ARM is incredibly established and effectively drives the mobile world. Still, the introduction of RISC-V could see ARMS position change as more companies see the advantages of using an open-source platform.

Read More

• New library leads to a huge reduction in code size for RISC-V applications

• First SoC FPGA development kit based on the RISC-V instruction set architecture

• Program designed to enable open, low power, programmable RISC-V solutions

Headline image By Derrick Coetzee (User:Dcoetzee) - Yunsup Lee holding RISC V prototype chipUploaded by Dcoetzee, CC0