SK Hynix announces memory roadmap – It’s all in the semiconductor!
02-04-2021 | By Robin Mitchell
Recently, SK Hynix outlined its memory roadmap which includes DRAM and FLASH. How does DRAM work, why is it a challenge to reduce in size, and what is SK Hynix planning for the future?
How does DRAM work?
Many memory technologies exist, and each one has its own advantages and disadvantages. For example, NAND FLASH is ideal for long-term storage with few writes, while SRAM is ideal for use in cache inside CPUs. DRAM, which stands for Dynamic RAM, is advantageous for use as an instantaneous memory storage solution due to its high-speed.
DRAM is nowhere near as memory dense as FLASH, nor can it hold its data when powered down. Furthermore, DRAM requires constant refresh cycles otherwise it will lose its held information. As such, DRAM is referred to as volatile memory.
DRAM technology stores information as an electric charge on capacitors. Inside a single bit of DRAM memory, a transistor is connected to a capacitor which allows for the capacitor to be charged and discharged (which represents a 1 and 0 respectively). To read a DRAM bit, the transistor has to discharge the capacitor, and this causes the bit to forget what it had stored. As such, whenever DRAM bits are read, they have to be written back to retain their data. Furthermore, since capacitors leak over time, the memory bits require frequent refresh cycles to retain their memory.
DRAM bits are arranged in arrays to maximise their density and ease of access, and the use of row selectors and column selectors enables individual addresses to be accessed.
What challenges does DRAM face?
As technology improves, the desire for increased memory sizes puts pressure on developers of memory technologies. DRAM is a memory technology that in particular struggles with size reduction for reasons not commonly met by other memory technologies.
To start, DRAM stores data as a charge on a capacitor, and therefore the greater this charge the longer the bit can be stored. However, reducing the size of transistors and capacitors on a semiconductor will result in smaller memory cells, and therefore the charge stored on each DRAM cell will be smaller. This can make it harder to detect stored bits as well as require faster refresh rates.
The second challenge faced by increasing DRAM capacity is increasing the size of the semiconductor chip itself. For n number of defects on a silicon wafer, larger die sizes result in less yield efficiency. As such, making larger DRAM dies will result in an increased cost at a reduced yield count.
The third challenge faced by DRAM is linked to the reduced capacitance of memory cells. If the charge stored on cells is reduced, it presents a challenge when trying to read the charge due to resistance in interconnections and routing wires.
What SK Hynix is planning
Recently, SK Hynix announced its roadmap to memory technologies of the future, and addressed the problems that current memory solutions faced.
To start, SK Hynix addressed DRAM scaling, and how it would plan to get around the issues previously discussed. The first challenge is retaining cell capacitance; reducing the dimensions of each capacitor results in a smaller capacitance, but this can be increased if the distance between the plates is reduced. However, this can only be achieved with stronger dielectric materials, as such, SK Hynix will explore better dielectric materials.
To solve the issue with patterning, SK Hynix will utilise EUV lithography, but this does not address problems faced with larger die sizes. However, the use of EUV allows for SK Hynix to make physically smaller components, and therefore maximise the number of bits per unit area. To solve the wire resistance issue, SK Hynix will explore low resistance wire technologies.
Reliability has also been identified as a key issue by SK Hynix. With the increasing use of automation (such as autonomous driving), components must be more reliable than ever before. As such, SK Hynix will look into developing highly reliable DRAM technologies such as increasing tolerance to soft errors.
But DRAM was not the only memory technology discussed; SK Hynix will also be improving NAND FLASH memory. Firstly, SK Hynix wishes to secure HARC etching technology which stands for High Aspect Ratio Contact. This technology allows for making deep channels in materials with little undercutting of the mask. SK Hynix will also look into better insulating materials for cell separation and will look into as many as 600 layers for maximised memory density.
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