Last year, Intel announced a new technology that has not been discussed widely in the electronics engineering space. What challenges do semiconductor fabs face when shrinking transistors, what is the latest technology, and could it be a temporary solution to increasing transistor counts?

What challenges do semiconductor foundries face when shrinking transistors?

A general rule of thumb that almost always holds true is that the more transistors integrated into a chip, the more it can do. For example, doubling the number of transistors potentially allows for a CPU to integrate more cores, more specialised hardware, and better bus technologies, all of which can help improve its performance.

Of course, reduced transistor size also corresponds to a reduced size of features, allowing for more complex circuits, including those entirely based in the analogue realm. For example, the ability to make smaller transistors also allows for smaller resistors, capacitors, and inductors, which can lead to more advanced analogue semiconductors.

Trying to reduce the size of features on semiconductors has been, and probably always will be, the primary goal of semiconductor foundries. In the past, this would have been achieved with a shorter wavelength of UV light, smaller mask technologies, better photoresists, and an improved understanding of etching chemistry.

However, the advent of nanometre devices has opened up semiconductor manufacturers to a whole new field of physics that routinely hinders transistor size reduction. One of these challenges is quantum tunnelling; an electron can essentially jump across an insulating barrier from one conductor to another. This causes issues when trying to reduce the size of the gate on MOSFETs as charges stored on the gate can jump across the insulation barrier into the channel, thereby increasing current consumption and reducing transistor performance.

Another challenge faced by foundries is the need for increasingly pure wafers. Larger silicon dies are somewhat more resilient to point defects and inclusions in their crystal lattice as their transistors are much bigger than the defects. However, transistors on the nanometre scale have features close in size to defects that can dramatically affect their performance. A single defect in a wafer can ruin a device (also keep in mind that there can be many thousands of defects across a wafer).

Intel’s 3D Nanoribbon stacking; a solution?

Last year, Intel announced its development of 3D nanoribbon stacking as a potential solution to increase the number of transistors of dies. Still, the stacking concept has not received as much attention as the nanoribbon technology itself.

Instead of trying to reduce the size of a transistor, one can instead stack multiple devices on top of each other. A good analogy to this is building up instead of out with houses; instead of building smaller houses, building towers can accommodate far more people per square area of land used. However, unlike residential towers, silicon dies are so thin that stacking multiple transistor layers does not increase the weight of the final device to any significant degree. Furthermore, stacking devices in this manner can actually be beneficial for performance by reducing the overall distance travelled by signals internally between circuits.

Intel is proposing with its nanoribbon transistor technology (where the gate is all around a channel) to stack NMOS and PMOS transistors vertically so that CMOS logic takes less space. This means complex logic elements can be significantly reduced in size (in terms of their footprint). Thus, more devices can be integrated onto a chip without adding additional vertical circuit levels.

Stacking technologies already exist, but they generally stack dies that use special interconnects between the dies. While this can be useful for increasing the number of transistors on a device, it comes with several challenges. One challenge is creating reliable connections between vertically stacked dies. Once dies are stacked on top of each other, they cannot be soldered internally or have metals deposited onto them. Whatever mechanism is used to connect to dies together must be able to form a reliable bond, not interfere with other circuitry, and allow for high-speed signals.

Are stacked CMOS circuits the solution?

While stacking CMOS devices is an excellent method for increasing the number of logic units on any given die, it is only a temporary solution. Once achieved, foundries are back to relying on reducing the overall size of transistors to increase transistor count. Furthermore, stacked transistors could make transistor reduction harder (as the z dimension now plays a more vital role in the device’s proper functioning).

It is not just Nanoribbons and their stacking that Intel is looking at for increasing transistor counts and improving device performance; MESO logic is a new contender for replacing CMOS. Magnetoelectric spin-orbit transistors utilise electron spin and magnetic fields to control the flow of current. Without going into great detail, they can be produced at extremely small sizes, use significantly less energy than standard CMOS devices, operate at high speed, and allow for unusual designs such as majority gates that can help with AI hardware.

Overall, the stacking of CMOS devices could provide the latest transistor technology with a sudden increase in transistor density, but this increase will be short-lived. If researchers are going to continue the trend in Moore’s Law, then new technologies that can be shrunk or stacked need to be explored.