2nm Chip Technology: Intel, Samsung, and TSMC's New Race

Intel, Samsung, and TSMC are at the forefront of a race to implement backside power delivery technology in their 2-nanometer nodes, aiming to enhance their competitiveness in the AI chip market. This innovative technology is poised to enhance chip efficiency by relocating the power delivery network to the backside of silicon wafers, a move set to streamline power efficiency, reduce interference, and improve overall performance. With Intel leading the commercialisation charge this year, followed by Samsung Electronics and TSMC gearing up for mass production in 2025, the industry is abuzz with anticipation for the transformative impact of backside power delivery. 

What challenges do engineers face when shrinking the size of transistors on semiconductor chips, how will the adoption of backside power delivery technology reshape the landscape of semiconductor manufacturing and design, and how might this advancement influence the development of future mobile application processors and AI chips?

Key Things to Know

• Intel Leads the Charge: Intel is set to commercialise backside power delivery technology this year with its PowerVia solution, aiming to enhance chip performance and efficiency.
• Competitive Edge: Backside power delivery technology improves power efficiency and reduces interference, crucial for AI applications and mobile processors.
• Industry Shift: Samsung and TSMC are also rapidly advancing their backside power delivery technologies, with Samsung aiming for mass production by 2025.
• Significant Impact: The adoption of backside power delivery is expected to transform semiconductor manufacturing, enabling more compact and efficient chip designs and driving innovation across the industry.

The Limits of Miniaturization: A Bottleneck to Future Device Advancement

The relentless pursuit of miniaturization has been the driving force behind the advancement of electronic technology, enabling the creation of smaller, more powerful, and energy-efficient devices. However, as engineers approach the fundamental limits of transistor size, the challenges posed by shrinking transistors are beginning to hinder further miniaturization. The combination of increased interference, reduced power efficiency, and limited space for circuits and power lines on the front side of chips is putting a bottleneck on the development of more advanced devices, raising concerns about the future of device miniaturization.

Technical Challenges in Miniaturization 

As transistors are made smaller and smaller, engineers face a multitude of technical challenges that, if not addressed, can have a ripple effect on the performance and scalability of electronic devices. The physical limitations of materials and the principles of physics, such as quantum tunnelling and heat dissipation, pose significant hurdles in the design and manufacturing of semiconductor chips. The crowding of circuits and power lines on the front side of chips exacerbates these issues, leading to reduced efficiency in power delivery and increased interference in signal transmission.

Traditional frontside power delivery methods, which have been the standard practice in the industry, are simply not suitable for the complexities of modern electronic devices. The close proximity of power lines and data transmission paths on the front side of chips results in crosstalk, noise, and signal interference, degrading the performance of electronic components and increasing energy consumption. The reduced space also leads to increased heat generation, further compromising the efficiency of power delivery and the overall functionality of the device.

Design Limitations and Integration Issues 

Furthermore, the limitations imposed by the frontside design of semiconductor chips hinder the integration of additional circuits and power lines, restricting the capabilities of electronic devices. As the density of transistors on the chip increases, fitting extra components, such as buffers, drivers, and control circuits, becomes a challenge, limiting the overall design flexibility and functionality of the device. The reduced space also reduces the potential for power efficiency enhancements, impeding the development of low-energy electronic systems that are essential for future electronic devices as they strive to meet increasingly stringent energy and carbon emission standards.

Intel's Backside Power Delivery: A Game-Changer for the Semiconductor Industry

The pursuit of smaller chip sizes and improved power efficiency has become a critical component in the competition among industry giants Intel, Samsung, and TSMC. The implementation of backside power delivery technology, which relocates the power delivery network from the front to the backside of silicon wafers, is at the centre of this competition, with all three companies vying to be the first to commercialise this innovative solution.

Challenges in Backside Power Delivery 

One of the primary challenges faced in achieving efficient backside power delivery is the integration of power and signal routing within the limited space of a chip. According to Intel's recent PowerVia test, decoupling power delivery from the signal path significantly enhances cell utilisation, achieving over 90% efficiency. This is crucial for supporting the increasing demands of AI and graphics applications, which require high-density and high-performance chip designs.

The advantages of backside power delivery are profound, enhancing chip performance while increasing power efficiency and reducing signal interference. With this technology, chips can be made smaller, a significant benefit for mobile application processors that require low energy consumption and compact designs. The use of backside power delivery also reduces the need for power distribution layers, lowering the total number of manufacturing steps and reducing the cost associated with semiconductor production.

Tackling Interconnect Bottlenecks 

Intel's innovative approach, as demonstrated in their PowerVia technology, also tackles the issue of interconnect bottlenecks. By moving power routing to the backside of the wafer, Intel addresses one of the most pressing challenges in chip design. This not only simplifies the manufacturing process but also improves thermal management, which is vital for maintaining performance and reliability in high-density circuits.

While Intel is poised to be the first to commercialise backside power delivery with its PowerVia solution, Samsung and TSMC are swiftly gaining ground. Samsung's advancement of its commercialisation timeline to 2025, initially planned for 2027, indicates a rapid pace in the company's development of backside power delivery technology. Reports suggest that Samsung may implement this technology starting with the 1.7nm process, with the 2nm process a primary focus. TSMC, however, has been silent on its plans, maintaining secrecy on its development progress.

Performance Enhancements with PowerVia 

Intel's advancements with PowerVia are not just limited to power efficiency. The test chip utilising PowerVia technology showed a 30% improvement in platform voltage droop and a 6% increase in frequency performance. These enhancements are significant for the overall performance of AI chips, as they ensure stable and efficient power delivery, which is critical for high-performance computing tasks.

Intel's developments in this area are particularly noteworthy, with the upcoming Arrow Lake desktop CPU set to utilise the Intel 20A node and PowerVia technology. The company's plans to unveil its first 2nm chips later this year further demonstrate its commitment to this innovative technology. The use of backside power delivery in the Intel 20A node will not only enhance chip performance but also increase power efficiency, a crucial factor in the industry's pursuit of reduced energy consumption.

Moreover, Intel's focus on decoupling PowerVia development from transistor advancements has allowed them to perfect this technology independently. This strategy ensures that PowerVia is optimised before integrating it with Intel's next-generation RibbonFET transistors, which will be introduced in the 20A process node. This methodical approach helps mitigate risks and ensures a seamless transition to more advanced semiconductor nodes.

Decoupling PowerVia Development

The competition among Intel, Samsung, and TSMC has intensified, with each company striving to achieve smaller chip sizes and improved power efficiency. The implementation of backside power delivery technology is a significant step in this competition, as it enhances chip performance, increases power efficiency, and reduces signal interference. While Intel is set to commercialise this technology first, Samsung and TSMC are swiftly gaining ground, with Samsung advancing its commercialisation timeline and TSMC maintaining secrecy on its development progress. The race for smaller continues, with the introduction of backside power delivery technology marking a new era in semiconductor manufacturing.

Backside Power Delivery Transforming Semiconductor Manufacturing

The semiconductor industry is at a crossroads, with the adoption of backside power delivery technologies gaining momentum as chipmakers like Intel, Samsung, and TSMC shift their focus towards enhancing power efficiency and reducing interference in their 2nm technology nodes. This shift away from traditional frontside power delivery systems is a response to the increasing challenges posed by the shrinking size of circuit designs, and the result could be game-changing for the AI chip market and the development of future mobile application processors (APs) and AI chips.

IEEE Recognition and Intel's Leadership 

The IEEE has identified backside power delivery as a crucial technology for the next generation of 2nm process nodes, and this technology is expected to provide a competitive edge by improving power efficiency and performance, which are essential for AI applications. With its PowerVia technology, Intel is poised to lead the way, aiming to integrate it into its upcoming 20A node and Arrow Lake CPU. The ability to deliver power efficiently and effectively will set a new standard in the industry, paving the way for enhanced performance and efficiency in AI chips.

The impact of backside power delivery on the development of future mobile APs and AI chips is significant, with the technology allowing for more compact and efficient designs. By reducing the size of chips, backside power delivery could significantly benefit mobile devices, enabling more advanced AI applications while improving power and frequency efficiency. The technology also promises to reduce signal interference and manufacturing challenges, leading to more robust and reliable AI applications across the industry.

Innovation and Miniaturization in Chip Architecture 

The adoption of backside power delivery opens new avenues for innovation in chip architecture and manufacturing processes, setting a foundation for further miniaturization and efficiency improvements in semiconductor technology. Early adoption and refinement of this technology by leading chipmakers could accelerate advancements across the entire semiconductor industry, leading to a new era of semiconductor manufacturing.

The semiconductor industry is at the forefront of technological innovation, and the shift towards backside power delivery technology is a significant step towards enhancing power efficiency, reducing interference, and driving further advancements in semiconductor manufacturing. As chipmakers like Intel, Samsung, and TSMC continue to advance in this field, the industry can expect to see compact and efficient designs, improved performance in AI applications, and new opportunities for innovation in chip architecture and manufacturing processes.