Emulation platform accelerates SoC verification tests up to 795X faster

Cadence Design Systems has announced that Global Unichip Corporation has selected the Cadence Palladium Z1 Enterprise Emulation Platform to accelerate SoC design and drive innovation in the semiconductor industry. By combining the emulation platform with Cadence Xcelium Parallel Logic Simulation, the company's engineers were able to apply more complex SoC verification test scenarios with full debug visibility, accelerating verification by up to 795 times. ?The emulation platform allowed the company to improve system-on-silicon verification and optimise hardware and software integration earlier in the verification process, securing high reliability. The compile abilities incorporated with the Palladium Z1 emulation platform also allowed the company to deliver more predictable turnaround times for full-chip emulation model builds. This helped their engineers to debug quickly and explore design changes 20X faster, which was not achievable with other design methodologies. “A high-performance ASIC verification solution is vital for driving our product innovations and business, and we need to continually strive to improve our overall product quality,” said Dr. Ken Chen, president at Global Unichip Corporation. “After comparing alternative solutions in the market, we selected Cadence’s Palladium Z1 Enterprise Emulation Platform for its effectiveness in ASIC verification productivity and use-model versatility. Adopting the Palladium Z1 emulation platform in conjunction with Xcelium Parallel Logic Simulation and the broader Cadence Verification Suite has enabled us to deliver flexible ASIC services that elevate our visionary IC customers to the next level of leadership in their respective markets.”