New VIP portfolio ensures SoCs meet the latest standard specifications

Cadence Design Systems, Inc offers 13 new Verification IP (VIP) solutions that allow engineers to swiftly and effectively verify their designs to fulfil the specifications for the latest standards protocols. The new VIP offerings enable customers to confidently produce their next-generation automotive, hyperscale data centre and mobile SoCs and microcontrollers whilst keeping pace with the latest industry standards, comprising Arm AMBA 5 CHI-f, Universal Chiplet Interconnect Express (UCIe), GDDR7, DDR5 DIMM, MIPI A-PHY and SoundWire I3S, and USB4 2.0 interfaces.

The new offerings customers a comprehensive verification solution for complex protocols. Its customers have access to a consistent API across all VIPs with complete bus function models, integrated protocol checks and coverage models, enabling rapid adoption.

All VIP solutions include Cadence TripleCheck technology, which offers users a specification-compliant verification plan linked to comprehensive coverage models and a test suite to provide compliance with the interface specification. The new VIP also supports the company's System-Level Verification IP (System VIP), which supplies SoC-level test libraries, performance analysis, and data and cache coherency checkers. Utilising the expanded System VIP portfolio, customers may experience up to 10X efficiency improvements compared to a manual process for SoC verification.

"The Cadence memory VIP is a critical part of our verification process and instrumental in the successful deployment of our memory PHY IP," said Ricky Lau, co-founder and CTO of The Six Semiconductor Inc. "Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards. The Cadence VIP offerings have significantly reduced our development time and increased the confidence of our customers."

"As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues," said Paul Cunningham, senior vice president and general manager of the System and Verification Group at Cadence. "With these 13 new VIP, Cadence is offering customers solutions to ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure."

The new VIP solutions are part of the wider company verification full flow, which incorporates Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio, and the Verisium AI-Driven Verification Platform. The verification full flow provides the highest verification throughput of bugs per dollar invested per day. The VIP solutions and verification full flow support the company's Intelligent System Design strategy, providing SoC design excellence.