First 3nm UCIe IP with TSMC CoWoS packaging launched

Alphawave Semi has launched the industry's first successful 3 nm silicon bring-up of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP with TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology.

The complete PHY and Controller subsystem was developed in collaboration with TSMC and targets applications such as hyperscaler, HPC and AI.

Using the foundry's CoWoS 2.5D silicon-interposer-based packaging, the fully integrated and highly configurable subsystem provides 8Tbps/mm bandwidth density, decreasing I/O complexity, power consumption and latency.

The IP supports multiple protocols, including streaming, PCIe, CXL, AXI-4, AXI-S, CXS, and CHI, allowing interoperability across the chipset ecosystem. It also integrates live per-lane health monitoring for enhanced robustness and enables operation at 24Gbps to provide the high bandwidth required for D2D connectivity.

"Achieving successful silicon bring-up of 3nm 24Gbps UCIe subsystem with TSMC's advanced packaging is a significant milestone for Alphawave Semi and underscores the company's expertise in utilising the TSMC 3DFabric ecosystem to deliver top-tier connectivity solutions," said Mohit Gupta, Alphawave Semi's SVP and GM, Custom Silicon and IP Gupta also stated the IP sets "a new benchmark in high-performance connectivity solutions."

The company's UCIe subsystem IP complies with the latest UCIe Specification Rev 1.1 and includes comprehensive testability and de-bug features such as JTAG, BIST, DFT, and Known Good Die (KGD) capabilities.