Vertically stacked GAA nanowire MOSFETs are a World first
07-12-2016 | By Paul Whytock
The CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs that feature a dual-work-function metal gate enabling matched threshold voltages for the n and p-type devices has been demonstrated for the first time by research centre IMEC.
This breakthrough is expected to advance the development of GAA nanowire MOSFETs which could replace FinFETs in 7nm technology nodes.
Such devices offer good electrostatic control which enables high-level CMOS device scaling and, in a horizontal format, they are a logical prolongation of FinFET technology. In this configuration the drive current-per-footprint can be optimised by vertically stacking multiple horizontal nanowires.
Earlier this year Imec scientists demonstrated GAA FETs based on vertically stacked 8nm diameter Si nanowires. These devices showed excellent electrostatic control but were fabricated for n and p-FETs separately.
An important aspect of the CMOS integration concept is the implementation of dual-work-function metal gates to allow the independent setting of the threshold voltages of the n and p-FETs. In this process p-type work function metal (PWFM) is deposited in the gate trenches of all devices, followed by selectively etching the PWFM down to the HfO2 from the n-FETs and subsequent deposition of the n-type work function metal.
Two different ESD protection diodes are being considered; a gate-structure defined diode and a shallow-trench isolation defined diode (STI diode). The STI diode was the better ESD protection device and demonstrated a good ratio of failure current over parasitic capacitance.
