Accelerating RISC-V solutions for developers

Imperas Software Ltd. has announced the latest product updates as a general release to all its customers and users. These product updates incorporate the latest models of RISC-V processors, ImperasDV processor verification solutions and virtual platform-based tools for software development and architecture exploration. Also updated is the free RISC-V instruction set simulator (ISS), riscvOVPsimPlus.

Imperas OVP RISC-V models support the complete range of the RISC-V specification, including support for ratified and stable, unratified specifications. The models are completely configurable for the full specification, including user preference of the version of each extension. The models, when employed with the Imperas simulators, are fast: typical performance under a normal software load is 500 million instructions per second! As well as generic RISC-V models, the Imperas OVP Processor Model Library supports models of processor IP from Andes, Codasip, Imagination, Intel, lowRISC, Microsemi, MIPS, NSI-TEXE, OpenHW Group, SiFive and Tenstorrent. The Imperas models can also be user-modified to add custom features, including instructions and CSRs.

The models are the key technology for the ImperasDV processor verification solution and the virtual platforms. ImperasD comprises the RISC-V reference model and verification IP to facilitate communication between the RTL simulation environment and the Imperas reference model subsystem and riscvISACOV SystemVerilog functional coverage modules. ImperasDV supports an asynchronous continuous compare verification methodology, which allows verification of complex processor features, including interrupts, Debug mode, privilege modes, multi-hart processors and processors with multi-issue and out-of-order pipelines.

Virtual platforms (instruction accurate software simulation) for software development are a must-have for software/systems of any complexity (AI/ML SoCs are a good example) or with quality, reliability, safety or security necessities. Imperas virtual platform products allow schedule reduction and enhanced debug and software analysis. Also, tools such as advanced tracing and profiling assist users with architecture exploration, including evaluating the impact of custom instructions on the RISC-V processor. Imperas products are also integrated within other standard EDA environments, such as SystemC, SystemVerilog, and well-known simulation and emulation tools from Cadence, Siemens EDA, and Synopsys.

“As RISC-V matures and adoption increases, the RISC-V ecosystem, including both hardware implementation and software development tools, becomes increasingly important to the success of individual RISC-V projects,” said Simon Davidmann, CEO, Imperas Software Ltd. “Imperas RISC-V Solutions are enabling our range of users, over 150 different organizations, to achieve their RISC-V project objectives.”