Embedded MRAM macro developed for high-performance MCUs

Renesas Electronics Corporation announced it has developed circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM, from now on MRAM) test chip with fast read and write operations. Fabricated using a 22nm process, the MCU test chip includes a 10.8Mbit embedded MRAM memory cell array. It achieves a random read access frequency of over 200MHz and a write throughput of 10.4MB/s.

As IoT and AI technologies advance, MCUs employed in endpoint devices are expected to produce higher performance than ever. The CPU clock frequencies of high-performance MCUs are in the hundreds of MHz, so to attain greater performance, read speeds of embedded non-volatile memory need to be increased to minimise the gap between them and CPU clock frequencies. MRAM has a smaller read margin than the flash memory used in conventional MCUs, making high-speed read operation more challenging. On the other hand, MRAM is faster than flash memory for write performance because it needs no erase operation before performing write operations. However, shortening write times is desirable for everyday use and cost reduction of writing test patterns in test processes and writing control codes by end-product manufacturers.

To address these challenges, the company has developed the following new circuit technologies to achieve faster read and write operations in MRAM.

Fast Read Technology: MRAM reading is generally performed by a differential amplifier (sense amplifier) to determine which memory cell current or the reference current is larger. However, because the difference in memory cell currents between the 0 and 1 states (the read window) is smaller for MRAM than for flash memory, the reference current must be positioned exactly in the centre of the read window for faster reading. The newly developed technology introduces two mechanisms. The first mechanism aligns the reference current in the centre of the window according to the actual current distribution of the memory cells for each chip measured during the test process. The other mechanism decreases the offset of the sense amplifier. With these adjustments, faster read speed is attained.

Furthermore, in conventional configurations, there is large parasitic capacitance in the circuits used to control the voltage of the bitline so it does not rise too high during read operations. This slows the reading process, so a Cascode connection scheme is introduced in this circuit to reduce parasitic capacitance and speed up reading.

Thanks to these advances, the company can achieve the world’s fastest random read access time of 4.2ns. Even considering the setup time of the interface circuit that receives the MRAM output data, it can realise the random read operation at frequencies over 200MHz.

Fast Write Technology: For the write operation, the high-speed write technologies for embedded STT-MRAM announced in December 2021 improved write throughput by first applying write voltage simultaneously to all bits in a write unit utilising a relatively low write voltage generated from the external voltage (IO power) of the MCU chip via a step-down circuit and then used a higher write voltage only for the remaining few bits that could not be written. This time, the company considers that because the power supply conditions employed in test processes and by end product manufacturers are stable, the lower voltage limit of the external voltage can be relaxed. Therefore, by setting the higher step-down voltage from the external voltage to be applied to all bits in the first phase, write throughput can be improved 1.8-fold.

Combining these new technologies, a prototype MCU test chip with a 10.8Mbit MRAM memory cell array was fabricated using a 22nm embedded MRAM process. Evaluation of the prototype chip confirmed that it achieved a random read access frequency of over 200MHz and a write throughput of 10.4MB/s at a maximum junction temperature of 125C.

The test chip also contains 0.3Mbit of OTP using MRAM memory cell breakdown to prevent data falsification. This memory can be utilised to store security information. Writing to OTP needs a higher voltage than writing to MRAM, making it more difficult to perform writing in the field, where power supply voltages are frequently less stable. However, by suppressing parasitic resistance within the memory cell array, this new technology also makes writing in the field possible.

These new technologies have the potential to dramatically boost memory access speed to over 200MHz, allowing higher-performance MCUs with embedded MRAM. Faster write speed will contribute to more efficient code writing to endpoint devices.