High-performance synchronous SRAMs integrate ECC for superior reliability

Cypress has introduced what it believes is the industry's highest-density synchronous SRAMs with on-chip error-correcting code (ECC). The integrated ECC feature enables the new 36Mb synchronous SRAMs to provide the highest levels of data reliability, simplifying designs for a wide variety of military, communication and data processing applications. Cypress plans to expand the family of high-performance synchronous SRAMs with ECC with additional densities later this year. Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress's new synchronous SRAMs performs all error correction functions inline, without user intervention, delivering best-in-class Soft Error Rate (SER) performance. The synchronous SRAMs with ECC are pin-compatible with current synchronous SRAMs, enabling customers to enhance SER and system reliability while retaining board layout. Additionally, the new SRAMs help reduce power consumption by as much as 36% over competing solutions, says the company. "Cypress is the worldwide market leader in synchronous SRAMs, and this new family of devices with on-chip ECC demonstrates our commitment to expanding our portfolio of standard synchronous, NoBL and QDR SRAMs," said Oliver Pohland, business unit director for Synchronous SRAMs, Cypress. "As with our entire SRAM portfolio, these new devices are backed by Cypress's best-in-class manufacturing and customer support." The new 36Mb synchronous SRAMs are currently available in industrial temperature grade in RoHS-compliant 100-pin TQFP and 165-ball BGA packages.