Multiple enhancements and general usability improvements for Vision line

Major enhancements to its entire Vision product line have been announced by Concept Engineering for designers of analog, digital, mixed-signal circuits, systems-on-chip (SoCs), and field-programmable gate arrays (FPGAs). StarVision PRO, RTLvision PRO, GateVision PRO, and SpiceVision PRO are customizable and scriptable debugging and visualization software tools that help electronic design engineers to easily understand, debug, optimize and document their designs. StarVision PRO provides analog, digital and mixed-signal debugging capabilities, customizable design rule checks and automated netlist pruning. RTLvision PRO is used for RTL debugging and intellectual property (IP) development. Designers use GateVision PRO for advanced netlist debugging of complex SoC netlists. SpiceVision PRO provides advanced exploration and debugging features for transistor-level and post-layout netlists. SpiceVision PRO's unique SPICE netlist visualization capabilities help engineers to analyze SPICE simulation results and allow easy location of circuit problems at the device level. "With version 6, we continue to improve our specialized product family with individual tools for specific circuit debugging problems," said Pascal Bolzhauser, product manager for Concept Engineering's Vision product line. "We have made specific enhancements to each tool and we also have incorporated multiple general usability improvements." Notable enhancements in the Vision product line are: 1 - Improved netlist pruning: In addition to Verilog and SPICE netlist export and pruning, StarVision PRO now also allows netlist pruning for the most common post-layout formats, DSPF and SPEF. 2 - Advanced post-layout debugging: Improved visualization and debugging of parasitic networks. 3 - API improvements: Improvements in the database API and GUI API allow even more sophisticated code to be developed and executed by the tool. 4 - Advanced batch processing: Enhanced batch processing capabilities allow more efficient processing of user-defined analysis and debugging tasks. 5 - Unified File Open Dialog: Makes it easier to load complex mixed-language SoC designs and libraries. 6 - Improved visual debugging capabilities such as: Smart connectivity lens view, improved schematic navigation history, and on-the-fly hierarchy exploration with built-in fold and un-fold controls.