New memory allocation soft IP for Intel's Altera FPGA devices

Synaptic Laboratories has launched its new memory allocation soft IP (SRAM-T001) for Intel's Altera FPGA devices. The product fills a long standing gap in the Altera Qsys development suite. It makes the finer-grain allocation of SRAM memories simple and can save up to c.50% of precious SRAM resources in every memory instantiation in Qsys and Altera devices. SRAM-T001 also delivers faster clock speeds in Qsys. Typically 5% to 30% faster for non-burst (i.e. burst-of-1) memory transfer requests, and typically 20% to 44% faster for BURST mode (i.e. for burst-of-8 memory transfer requests that are issued when burst mode is enabled on one or both of the processor’s ports). SRAM-T001 can also reduce circuit area. SRAM-T001’s integrated burst-of-8 to burst-of-1 converter is 3.5x smaller than the Altera burst converter logic automatically embedded in the Avalon Merlin Interconnect by Qsys, when using burst mode. This reduces the circuit area cost of using the popular burst mode. It saves 64 ALM (128 LE) for each bus master port of the Nios II/fast core that has burst mode enabled. Every reduction in circuit area is important in area constrained designs, for projects that are targeting the lowest possible cost and size FPGA device, including for IoT. The SRAM-T001 is fully supported in Qsys and the Nios II development environment. It eliminates the need for individual designers to attempt to find work arounds to fine grain memory allocation. Work-arounds that cost extra time, effort, extra circuit area and can result in slower clock speeds and wasted memory. The highly-configurable SRAM-T001 is designed to replace the use of Altera 'on-chip SRAM' in Qsys projects, says the company.