Fast ISP flash configuration for ARM-Based FPGA SoCs

XJTAG has extended its capability to their high-speed In-System Programming (ISP) technology, XJFlash. This brings the benefits of XJFlash to memory devices connected to the processor sub-system of dual ARM-Cortex-A9 based FPGAs. Using the software customers could experience programming times as much as 20 times faster than existing solutions when configuring memory attached to the processor sub-systems of the industry’s leading FPGA SoCs, such as Xilinx Zynq and Altera Cyclone V SoCs, which feature dual ARM Cortex-A9 processors. The use of FPGAs with integrated processor sub-systems is increasing. While these sub-systems are fully integrated into the FPGA fabric, they feature their own, dedicated, external non-volatile program memory, connected to the physical pins of the FPGA. Configuring these memories in both development and production environments is normally a slow and often complex process. With the software these memories can now be configured simply and at high speed through the JTAG port of the FPGA, without the need for any additional PCB connections. With this latest development, the software is now able to access and configure memory devices connected to a wider range of FPGAs. This will significantly decrease the time taken to configure on-board memory during development, production and rework. Support for the ARM Cortex-A9 based SoCs extends to partial reconfiguration and optimised erase, delivering further productivity benefits. This enables memory devices to be partially erased and reconfigured without having to reprogram the entire device and also minimises the erase time when regions of a device are already blank.