HDMI 2.0 chips improve switching, signal integrity and connectivity of video

L2Tek has announced a new family of video ICs from Explore Microelectronics. Aimed at companies designing and manufacturing digital and analogue AV broadcast and switching equipment or high-end home-theatre applications, the latest series of HDMI 2.0 switchers, splitters and repeater chipsets supports video output at 12bit 1080 full HD, full 3D, HDR and 4K2K 60Hz resolutions. Their products include the EP9462S, a HDMI 2.0a 4-IN 2-OUT repeater with HDCP 2.2 in a 128-pin LQFP package. The chip supports four inputs to two outputs matrix switching with HDCP repeater function. The chip also converts HDCP 1.4 to HDCP 2.2 and HDCP 2.2 to HDCP 1.4. Dual-in to single-out conversion in left/right inputs is another feature. In its new line of splitters, the EP9164S is a four-port DVI/HDMI 1.4b/HDMI 2.0a solution with integrated HDCP 1.4 and HDCP 2.2 decryption/encryption engines. The chip receives DVI/HDMI 1.4b/HDMI 2.0a inputs, processes HDCP 1.4 or HDCP 2.2 decryption and encryption again, then transmits the data to four DVI/HDMI 1.4b/HDMI 2.0a ports. The IC also supports conversions from HDCP 1.4 to HDCP 2.2 (and vice versa). Switchers also benefit from HDMI 2.0 system compatibility. For example, the new EP91A6S is an HDMI 2.0 1-IN 1-OUT repeater with HDCP 2.2. The chip supports HDMI input, HDMI output, HDCP decryption, audio outputs, audio inputs and HDCP re-encryption in repeater mode. The chip also supports HDCP 1.4 to HDCP 2.2 and HDCP 2.2 to HDCP 1.4 conversions. It also provides 6G to 3G conversion that convert 4K2K 60Hz YCC444 format to YCC420 format to reduce bandwidth. The chip supports HDMI output to be regenerated from a LPCM audio source or the by-passed audio from the selected HDMI input port while its integration with an eFlash MCU also makes user applications easier to implement. In addition, the new EP9261E is a 6GHz HDMI 2.0 2-IN 1-OUT with an integrated equaliser and jitter-clean capability for extended cable length. The chip uses re-sample and re-drive architecture, which re-samples data at the receiver side and re-drives data at the transmitter side. This architecture will not pass through noise from input to output, and therefore provides reliable transmission. The chip also supports four ports of on-chip EDID RAM and programmable passive/active DDC switches to lower the system cost.