Ultralow jitter clock family ideal for high-speed data converter clocking applications

Analog Devices is now offering the LTC6952, LTC6953, LTC6955 and LTC6955-1 family of low jitter, high-performance clock generation and distribution devices supporting JESD204B subclass 1 clocking applications up to 7.5GHz. These products are perfect for high-speed data converter clocking applications, with a scalable architecture to produce thousands of synchronised low jitter clocks, each with a complementary SYSREF signal. The LTC6952 is a high-performance, ultralow jitter, JESD204B clock generation and distribution device. It includes a PLL core, consisting of a reference divider, PFD with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. The device’s eleven outputs can be configured as up to five JESD204B subclass 1 device clock/SYSREF pairs, and one general purpose output, or simply 11 general purpose clock outputs for non-JESD204B applications. Each output has its own independently programmable frequency divider and output driver. All outputs can be synchronised and set to exact phase alignment using single coarse half-cycle digital delays and fine analogue time delays. The LTC6953 is the clock distribution function of the LTC6952. The LTC6955 is an 11 output fanout buffer with a parallel interface that chooses one of three states per output group: in-phase, 180-degrees out of phase, or power-down. The LTC6955-1 is the same as the LTC6955 except one output has an integrated ÷2. All devices are provided in a 52-lead, 7mm × 8mm plastic QFN package. The device is rated for operation from –40C to 125C junction temperature. Unused outputs can be powered down when not in use.