CompactPCI processor boards feature 11th Gen Intel Core and Xeon processors

EKF Elektronik will launch two new 3U CompactPCI processor boards with 11th-generation Intel Core and Xeon processors (codename Tiger Lake H45) at embedded world 2023. The boards will be offered in two variants: the first is a CompactPCI Serial design, and the second supports CompactPCI Classic and CompactPCI PlusIO. The latter supports the classic parallel PCI bus, for which many COTS and proprietary expansion cards are still available. This allows developers of CompactPCI-based systems to implement any CompactPCI system design and secure their investment in this PICMG standard long into the future. The new boards will be provided until at least 2032 – just as the existing CompactPCI CPU boards with 7th generation Intel Xeon E3 v6 processors (codename Kaby Lake), which the company also provides for all three CompactPCI sub-specifications.

“Support for the PCI bus is essential for older CompactPCI system designs, yet some vendors are withdrawing from this market. The announcement that EKF Elektronik will continue to support the PCI bus for new CompactPCI designs, therefore, sends an important message to many users: They can safeguard their investment in this legacy technology for many more years, continue to upgrade their system designs with the latest processor technology, and reap all the benefits that come with it,” explains Manuel Murer, business development manager at EKF Elektronik.

The advantages of these upgrades include efficiency, higher energy, higher processor-integrated security and computing power, up-to-date software support, and all support for AI and the latest graphics features to deliver the best possible user experience. As 11th Gen Intel Core and Xeon processors no longer support PCI natively, the company has installed a software-transparent PCIe-to-PCI bridge on the processor boards with CompactPCI Classic and CompactPCI PlusIO support. This enables developers to port existing applications to the new boards seamlessly.

CompactPCI PlusIO users will discover a new J2 connector on the new CompactPCI PlusIO (PICMG 2.30) boards, which is footprint-compatible with the CompactPCI Classic (PICMG 2.0) specification. This change was required because the J2 connector specifically developed for PlusIO has been discontinued. But there is no necessity to redesign the backplane. The only restriction is that high-speed backplane transfer is limited to 2.5GT/s for PCIe Gen 1 and 1.5Gbit/s for SATA. It is possible to use the full bandwidth depending on the application and system. The CompactPCI‘s PCI bus can be employed in the usual bandwidth of up to 133Mbyte/s.

Embedded world, Hall 1, Booth 1-406, 14-16 March 2023.