First fully customisable RISC-V IP cores for large amounts of data

Semidynamics has released the world’s first, fully customisable, 64-bit RISC-V family of cores that are excellent for handling large amounts of data for applications, including AI, ML and HPC. The cores are process agnostic, with versions currently supplied down to 5nm.

Semidynamics CEO and founder, Roger Espasa, explained: “Until now, RISC-V processor cores had configurations that were fixed by the vendor or had a very limited number of configurable options such as cache size, address bus size, interfaces and a few other control parameters. Our new IP cores enable the customer to have total control over the configuration, be it new instructions, separate address spaces, new memory accessing capabilities, etc. This means that we can precisely tailor a core to meet each project’s needs so there are no unrequired overheads or compromises. Even more importantly, we can implement a customer’s ‘secret sauce’ features into the RTL in a matter of weeks, which is something that no one else offers. Every designer using RISC-V wants to have the perfect set of Power, Performance and Area along with unique differentiating features, and now, for the first time, they can have just that from us.”

The first in the family, offered for licensing now, is the Atrevido core. This provides out-of-order scheduling combined with the company’s proprietary Gazzillion technology so that it can handle highly sparse data with long latencies and with high bandwidth memory systems typical of current machine learning applications. Effectively, Gazzillion technology excludes the latency issues that may occur when employing CXL technology to provide far-away memory to be accessed at the supercharged rates it was developed to provide.

For demanding workloads, such as HPC, the Atrevido core supports large memory capacities with a 64-bit native data path and 48-bit physical address paths. Espasa added: “We have the fastest cores on the market for moving large amounts of data with a cache line per clock at high frequencies even when the data does not fit in the cache. And we can do that at frequencies up to 2.4GHz on the right node. The rest of the market averages about a cache line every many, many cycles, which is nowhere near our one every cycle. So, if the application streams a lot of data and/or the application touches very large data that does not fit in cache, we have the best RISC-V cores on the market for your use case.”

With its complete MMU support, Atrevido is also Linux-ready comprising supporting cache-coherent, multi-processing environments from two and up to hundreds of cores. It is vector ready, supporting the RISC-V Vector Specification 1.0 and the upcoming Semidynamics Open Vector Interface. Vector instructions densely encode large numbers of computations to lower the energy utilised by each operation. Vector Gather instructions support sparse tensor weights efficiently to assist with ML workloads.

He concluded: “We have been in stealth mode while we created the core architecture that the RISC-V community really wants – one with full customisability, not just a few tweakable settings. No one else has such a complex RISC-V core that can be totally configured to perfectly meet the specific needs of each project rather than having to use an off-the-shelf core and compromise.”