IMEC Demonstrates Buried Power Rails in FinFET CMOS
17-03-2021 | By Robin Mitchell
Recently, IMEC announced functioning devices using a new technique of burying power rails below active devices. What is a buried power rail, what did IMEC demonstrate, and why are buried power rails advantageous?
Semiconductor Routing Challenges
Designing semiconductor devices presents a whole range of different challenges including quantum tunnelling, causing current leakage, overheating devices, propagation delay, and feature sizes. Once the active components of a semiconductor are designed (i.e. transistors), the remaining layers are used to route signals and power. This stage is very similar to routing a PCB, and as such can suffer from similar problems.
Generally, routing power rails is the last step in a design as routing signals takes priority (especially in high-frequency circuits), and as such is given the topmost layer (called M1). As a result, power rails can be far from their active components while the use of many interconnects introduces resistance, inductance, and reflections.
What is a buried power rail?
A buried power rail is a power rail found inside the semiconductor substrate instead of on a metal layer. The rail itself is constructed to run underneath the active layer where semiconductor components are found (i.e. transistors and diodes). The concept of buried power rails is still limited to the laboratory and not currently used by commercial devices.
IMEC Demonstrates FinFET CMOS with Buried Power Rails
Recently, IMEC demonstrated silicon devices using CMOS technology that incorporates buried power rails. The demonstration utilises FinFET CMOS to show that buried power rail (BPR) technology can work with modern technologies.
One of the concerns of using BPR technologies in semiconductor devices is the active layer's interference when embedding BPRs. Since the layer sits below the active layer, and these layers are created one after the other, there is a chance that device performance can worsen as a result of stress, degradation, and metal contamination. However, the demonstration by IMEC shows that these worries can be avoided to create fully-functional active devices down to the 3nm scale.
The BPRs developed by IMEC are made from Tungsten (W), and via interconnects to this layer used Ruthenium (Ru). The effectiveness of the BPRs was further displayed after 900 hours of continual use at 330°C at a current of 4MA/cm2 with no electromigration failures being observed.
Cross-section of IMEC device – Image courtesy of IMEC
What advantages do buried power rails have?
After discovering that the BRPs are made of tungsten, the question of resistance immediately comes to mind. Copper is a highly conductive element, and as such has a low resistance, but tungsten has a resistance almost four times higher than copper. As such, tungsten rails would have an additional power loss of 4 times that of copper, and therefore 4 times greater energy loss.
However, while tungsten may have a greater resistivity than copper, using BRPs provides advantages not possible with M1 power routing. Routing power rails below the active layer offers a shorter routing distance between active devices and power rails (remember that CMOS technology requires a direct connection to power rails VDD and VSS). As such, the total length of wire between the power and individual active devices is reduced.
The second advantage is that designers are given more freedom on routing layers by moving power routing below the active devices. As such, signal connections can be reduced in length which allows for greater speed of operation. A secondary study on BRPs has confirmed such advantages and has stated that grid power distribution can improve SRAM by 28.2%.
Buried Power Rails are still in development, and add an entirely new production step to a semiconductor. But their advantages are clear with reduced power rail length, improved efficiency, and a more compact design.
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