Interconnect designer and SiP reduces design time by 60 percent

Cadence Design Systems has announced that Faraday Technology has used Cadence OrbitIO interconnect designer and Cadence SiP Layout to reduce its packaging design time by 60 percent over its previous methodology. OrbitIO and SiP Layout enable automated IC/package/PCB interconnect design and optimization. This capability can better optimize the interconnect pathways for routing and signal/power integrity performance as compared to the current methods of using static spreadsheets. The multi-substrate interconnect pathway design optimizes design performance and minimizes substrate complexity and cost by allowing trade-off exploration and decisions early in the process. By implementing this process, Cadence is able to reduce the typical spreadsheet-based bump/ball map planning studies from days/weeks with multiple iterations to just a few hours with little to no iterations using the single multi-fabric environment of the OrbitIO interconnect designer, says the company. “Die bump planning and optimization is a critical part of our SoC and ASIC design process in order to meet our performance goals,” said Jim Wang, senior associate vice president, Faraday. “Using OrbitIO helps us achieve our goals in an efficient manner and enabled us to reduce design time by up to 60 percent, while delivering the quality of results our customers expect.” “With our customers’ needs as top priority, we enhanced the OrbitIO Interconnect Designer, which contributed to a fully automated methodology for optimizing cross-domain interconnect pathways,” said Saugat Sen, vice president of R&D, PCB and IC Packaging Group, Cadence. “The result is a streamlined design flow that leads to reduced design cycles and lower product development costs.”