Test solution enables support for safety-critical SoC designs

The Cadence Modus Test Solution from Cadence Design Systems now supports the ARM memory built-in self test (MBIST) interface, enabling customers to efficiently create safety-critical system-on-chip (SoC) designs using high-performance ARM processors. To demonstrate the success of the collaboration, Cadence and ARM have completed silicon validation using an ARM Cortex-A73 processor in conjunction with the Test Solution’s automatic test pattern generation (ATPG) and diagnostic capabilities. Through the company’s support of the ARM MBIST interface, customers can deliver innovative SoC designs to market faster and with better power, performance and area. For example, the Test Solution provides ARM MBIST interface users with the option for programmable MBIST to use a single bus to service multiple memories with one MBIST controller. The solution utilizes the ARM MBIST interface to reduce the impact of MBIST on critical timing paths to and from memories in functional operation and for a higher quality at-speed test. Finally, the solution provides a physical-to-logical mapping capability, which reduces the need for manual, error-prone work. “The Cadence Modus Test Solution supports the ARM MBIST interface and its many benefits,” said Teresa McLaurin, fellow and director, technology services group, ARM. “One feature is automation of the physical-to-logical mapping capability that bridges the definition of logical memories to a customer’s unique physical memory configuration, simplifying the task of integrating MBIST for ARM IP in their products.” “We launched the Modus Test Solution earlier this year to address escalating manufacturing test costs. Its patented 2D Elastic Compression technology delivers up to 3X reduction in manufacturing test costs,” said Paul Cunningham, vice president of research and development in the Digital and Signoff Group at Cadence. “Since then, we’ve continued to expand the Modus Test Solution’s technical capabilities, and by working with ARM, we’re enabling customers to easily incorporate ARM IP and Cadence flows in order to bring competitive, safety-critical SoCs to market.” The solution is a comprehensive next-generation physically aware design-for-test (DFT), ATPG and silicon diagnostics tool. Using the solution, customers can experience up to 3X reduction in test time using its patented physically aware 2D Elastic Compression architecture, without any impact on fault coverage or chip size.