Virtual emulation adapter accelerates software bring-up time by up to three months

Cadence Design Systems has announced the release of the new VirtualBridge Adapter, a virtual emulation technology that accelerates software bring-up in pre-silicon verification versus RTL simulation. The adapter allows software engineers to start their pre-silicon verification tasks with the Cadence Palladium Z1 Enterprise Emulation Platform up to three months earlier, complementing their traditional in-circuit emulation use model. The adapter is available as a software add-on to the platform. The adapter expands the customer’s use model and enables teams to extract the most value out of their hardware investment. It allows engineers to interface virtually with peripherals, providing the flexibility to run jobs without physical constraints, and improving debug efficiency by augmenting physical debug with virtual debug capabilities for repeatable debug and controlled error injection. Through a balanced distribution of verification tasks between in-circuit and virtual emulation and smooth integration with other company tools such as Palladium Hybrid, design teams can maximize their hardware investments and reduce overall software bring-up time. “Virtual emulation is a key capability for software-driven hardware verification and system validation,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital and Signoff Group, and the System and Verification Group at Cadence. “Coupled with our Palladium Z1 emulator, the VirtualBridge Adapter enables our users to further shorten their development cycle as they are pressed to bring quality products to market quickly.” “Cadence’s VirtualBridge Adapter enables us to implement complex, multi-GPU configurations with ease,” said Narendra Konda, director of hardware engineering at NVIDIA. “It complements the Palladium Z1 platform’s in-circuit emulation testing capability and enables us to run our applications and drivers earlier in our development cycle.”