Highly integrated, low-power clock ICs simplify timing for demanding designs

Silicon Labs has introduced a new family of high-performance clock generators offering the industry’s most highly integrated timing solution for 10/25/100G applications. The new Si5332 clock family leverages Silicon Labs’ proven MultiSynth fractional clock synthesis technology to deliver a timing solution that provides best-in-class frequency flexibility and jitter performance of 230fs RMS. Multiple device options spanning six, eight and 12 clock outputs enable clock tree consolidation for demanding applications including hyperscale data center switches, servers, storage, networking, small cells, broadband, broadcast video, multi-function printers and industrial applications. Complex devices such as Ethernet switches, high-speed switch fabrics, network processors, server SoCs and FPGAs combine data path processing, CPU functions and multiple serializers/deserializers (SerDes) into a single IC. As a result, these devices require a diverse combination of reference timing. 10/25/100G SerDes have stringent jitter requirements, often requiring clocks with <300fs RMS maximum jitter performance. CPU phase-locked loops have lower jitter requirements but often use spread spectrum clocking to minimize EMI. Unlike traditional timing solutions that use a mix of crystal oscillators, buffers and fixed-frequency clock generators, the device clocks generate all SerDes, processor and system clocks in a single-chip device while providing significant jitter margin, enabling system developers to simplify clock trees and design with confidence. “Hyperscale data centers are quickly migrating from 10G to 25G, 50G and 100G Ethernet to accelerate data transfer and network efficiency. This new investment cycle is spurring equipment manufacturers to upgrade switch and access ports to higher speeds and to adopt higher performance timing solutions,” said James Wilson, senior marketing director for Silicon Labs’ timing products. “By choosing Silicon Labs’ Si5332 any-frequency clocks, system designers can optimize their clock tree designs without compromising timing performance.”