PCI Express Gen 5 clocks and buffers lead in performance and power

Silicon Labs has introduced a comprehensive portfolio of timing solutions providing best-in-class jitter performance to satisfy the latest generation PCI Express (PCIe) 5.0 specification with notable design margin. The Si5332 any-frequency clock family generates PCIe Gen 5 reference clocks with jitter performance of 140fs RMS, optimising PCIe SerDes performance while satisfying the Gen 5 specification with margin. The clocks generate any mixture of PCIe and general-purpose frequencies, allowing clock tree consolidation across a wide variety of applications. The company also provides the Si522xx PCIe clock generators and Si532xx PCIe buffer families, which can provide two, four, eight, or twelve PCIe Gen 1/2/3/4/5-compliant outputs, making them an excellent fit for clocking a broad mixture of PCIe endpoints in data centre applications. The company’s new clock devices are fully compliant with PCIe Gen 5 Common Clock, SRNS and SRISarchitectures. Despite PCIe Gen 5 having more stringent jitter demands, The company's new products do not need discrete power supply filtering components, simplifying PCB layout while assuring board-level noise does not degrade clock jitter performance. Board designers can seamlessly migrate existing PCIe Gen 1/2/3/4 designs with drop-in compatible Si5332, Si522xx and Si532xx clocks to easily upgrade current designs to take advantage of faster PCIe serial interfaces. “Silicon Labs is committed to providing best-in-class timing solutions to ease the migration to higher-speed PCI Express,” said James Wilson, general manager of timing products at Silicon Labs. “Data centre designers want to take advantage of PCIe Gen 5 to increase interconnect speeds between the CPU and workload accelerators, including GPUs, FPGAs and dedicated accelerator solutions. Increasing the bandwidth among networking, storage and AI resources will help enable the industry transition to 400G Ethernet.”