31-03-2020 | Segger | Design & Manufacture
SEGGER has strengthened its position regarding the RISC-V instruction set architecture. The company’s products are currently fully compatible with SiFive’s RISC-V processor cores, and now its J-Link probes provide support for the new SiFive Insight debug/trace solution. This includes the company’s latest Nexus-based trace implementation, which allows ongoing monitoring and recording of processor instruction execution.
Via the company's J-Link PLUS, PRO and ULTRA debug probe options, as well as the accompanying Ozone debugger and performance analysis software package, engineers are now capable of taking full advantage of SiFive Insight employing on-chip trace functionality. Among the relevant options included within the debug probes is a backtracing ability (where the full execution history can be readily accessed and stepped through backwards). More advanced features, like code coverage and profiling, can also be used - based on the execution counters processed by the J-Link software. The debug software package can consequently generate detailed code coverage reports for software validation purposes.
“The continued support from SEGGER is a great asset to the RISC-V ecosystem, and the swift adoption of SiFive Insight is of great benefit to chip designers,” says Drew Barbier, director of Product Marketing at SiFive. “SEGGER has supported SiFive Core IP since 2017 and continues to be a valued partner in the expansion and adoption of RISC-V for embedded solutions. We look forward to continued cooperation as the RISC-V ecosystem continues to grow and evolve.”
“SiFive continues to innovate with solid offerings for the global RISC-V community,” adds Rolf Segger, founder of SEGGER. “We are proud to support its team’s efforts by offering high-quality development tools and ensuring that the exciting new features they are introducing can be fully leveraged using our industry-leading Ozone debugger software and J-Link debug probe products.”
