Die-to-die connectivity IP addressing supports organic substrate packaging

Cadence Design Systems offers its silicon-proven Cadence UltraLink D2D PHY IP on the TSMC N7 process. Test silicon on the process with full silicon characterisation data is now offered, an important milestone for very high-speed, advanced IP. Extensive silicon validation is required to guarantee design margins, performance across all process corners, BER, insertion loss and maximum transmission speed. For the N6 process, re-characterised silicon data is offered.

System advances in accelerated computing platforms including CPUs, GPUs and FPGAs, heterogeneous SoCs for AI acceleration and high-speed networking/interconnects have all driven chip integration to unprecedented levels. This demands more complex designs, larger die sizes and fast adoption of the most advanced geometries. To manage the economics of advanced silicon and the ever-increasing monolithic die size, die-to-die connectivity has become more important as multi-die designs employing advanced packaging have become very common.

“We’re pleased to see the result of our latest collaboration with Cadence in delivering Cadence’s D2D PHY IP across several TSMC advanced processes,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Cadence’s leading-edge SerDes IP and TSMC’s advanced process technologies helps our customers unleash their silicon innovations for emerging cloud computing, AI, 5G and hyperscale data centre applications.”

“To help our mutual customers achieve success in advanced SoC designs for cloud computing applications, we’ve enabled our UltraLink D2D PHY IP in multiple TSMC advanced processes: First in N7 and N6, with a quick follow-on with N5 later this year,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “To address our customers’ rapidly evolving requirements, we continue to invest in both PAM4 and NRZ SerDes IP. The UltraLink D2D PHY IP is a critical technology delivering high bandwidth, low latency and power while enabling the proliferation of heterogeneous designs and integrated packaging solutions.”