Family of reference designs can reduce design costs and time by up to 30%

Sondrel has released a family of reference designs that could lessen design costs, risk and time by up to 30% when compared to starting from scratch. The company has drawn on its expertise in designing hundreds of ASICs to produce a set of key reference designs that each offer a fast design time for high growth markets.

“In a given application area, there is always considerable duplication in the design of each ASIC as there is a lot of communality in the interconnections and supporting IP that forms the architecture of the device,” explained Graham Curren, Sondrel’s CEO. “Rather than start from scratch with each new design, we have created reference designs that distils our experience of designing the architecture for such chips to create reusable IP platforms. Onto this, we add the customer’s IP with some customisation to create a bespoke solution for that customer. This reduces the overall design costs and risk as our IP platform is tested and ready to use, which also means that the time to market is reduced as well. We estimate that this approach, which we are calling Architecting the future™, will provide time and cost savings of up to 30% for customers.”

Ian Walsh, Sondrel’s VP Worldwide Sales, added: “Potential customers for ASIC are often concerned that a custom ASIC will be very expensive. Our semi-custom, reusable IP platforms not only reduce costs but also makes it much easier to give indicative costs for customers right at the start so that they can see how cost-effective and affordable our solution will be. Our experience with each reference design means that we can estimate the ballpark costs for design, IP licensing, foundry, test, qualification and packaging right through to the total cost per unit. Just what is needed for budgeting a new project and deciding its viability.”