21-04-2022 | Cadence | Subs & Systems
Cadence Design Systems, Inc. has released the Cadence High-Speed Ethernet Controller IP family, which allows total Ethernet subsystem solutions up to 800G together with Cadence SerDes PHY IP in 7nm, 5nm and 3nm process nodes. Optimised for PPA, the low-latency, high-speed controller IP extends its Ethernet Controller IP portfolio and is ideal for a wide array of Ethernet applications in the next-generation cloud, AI/ML, and 5G infrastructures.
The new controller family provides different aggregated bandwidths for 100G, 200G, 400G and 800G Ethernet.
Along with its leading-edge 112G/56G and other Ethernet SerDes PHY IP, the company offers full subsystem deliveries with integrated PHY and controller that allow customers to facilitate integration and streamline their SoC designs. Silicon proven in AI/ML customer applications, the integrated subsystems offer optimal PPA.
“The exploding bandwidth demand from cloud, AI/ML and 5G has driven Ethernet protocols to evolve and has accelerated 800G market adoption,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “Cadence continues to invest in design and interface IP that addresses our customers’ rapidly evolving requirements. The Cadence high-speed Ethernet subsystem solutions with best-in-class PHY and feature-rich controller IP further solidify our leadership position with high-performance connectivity IP offerings.”
The family and integrated subsystem solutions extend the company's Ethernet IP portfolio and support its Intelligent System Design strategy by facilitating SoC design excellence.
