Companies team up to package cryo chips

Following on from sureCore’s launch of a range of cryogenic IPs following the successful evaluation of test chips in 180nm and 22nm process nodes, it has revealed that it has teamed with Sarcina, who designed a custom package specifically for use at cryogenic temperatures.

Paul Wells, sureCore’s CEO, explained, “This represents another critical step in our programme to make Cryo-CMOS available for the Quantum Computing (QC) ecosystem. Our CryoMem range of memory IP is silicon-proven in addition to validating our library recharacterisation service. We are also offering a range of cryogenic design capabilities to help QC companies design the control/interface chips which need to be migrated into the cryostat alongside the qubits. Reliable, robust, cryo-ready chip packaging is a necessity in these harsh, low-temperature environments, and to ensure this, we partnered with Sarcina, whose specialist package design expertise is second to none.”

Larry Zu, Sarcina’s CEO, added, “We have developed a reputation as the ‘go-to’ design expert for companies needing to push the boundaries of current packaging technology. Whether this be for complex multi-chip 3D solutions, or, as in this case, for extreme low temperature operation, our experience and know-how allowed us to develop a custom BGA package specially for cryogenic temperatures.”

The IUK-funded consortium is a complete ecosystem of companies with the expertise and core competencies needed to develop cryo-tolerant semiconductor IP. The aim of the project is to develop and prove a suite of foundation IPs that can be licenced to designers, permitting them to create their own Cryo-CMOS SoC solutions. By doing so, their competitive edge in the Quantum Computing space will be dramatically accelerated.

sureCore has exploited its state-of-the-art, ultra-low power memory design skills to create embedded SRAM, a vital building block for any digital sub-system, that is capable of operating from 77K (-196C) down to the near absolute zero temperatures needed by QCs. Also, both standard cell and IO cell libraries have been re-characterised for operation at cryogenic temperatures, thereby allowing an industry-standard RTL to GDSII physical design flow to be readily adopted.

A key barrier to QC scaling is being able to collocate ever increasingly complex control electronics close to the qubits that must be accommodated at cryogenic temperatures in a cryostat. In doing so, it is crucial that the control chip power consumption is kept as low as possible to ensure that excess heat is kept to a minimum so it does not cause additional thermal load on the cryostat. Here, sureCore’s low-power design expertise proved pivotal.

Current QC designs have the control electronics located outside the cryostat, as modern semiconductor technology is only qualified to work down to -40C. As the temperature is lowered close to absolute zero, the operating characteristics of the transistors change markedly. Measuring, understanding and modelling this behavioural change over the past months showcases the potential to build interface chips that can control and monitor qubits at cryogenic temperatures.

At the moment, expensive, bulky cabling connects room temperature control electronics to the qubits housed in the cryostat. Enabling QC developers to be able to exploit the fabless design paradigm and create their own custom cryogenic control SoCs, which can be housed with the qubits inside the cryostat, is a game-changer that will swiftly allow QC scaling. Immediate benefits include cost, size and, most importantly, latency reduction. The next step will be characterising the demonstrator chip at cryo temperatures to refine and validate the models further and improve performance.