Infineon releases second-generation non-volatile SRAM – How does it work?
04-04-2021 | By Robin Mitchell
Recently, Infineon announced the release of its second-generation non-volatile SRAM. What features does the new SRAM provide, how does it work, and what applications could it be used in?
Infineon Releases New Non-Volatile SRAM
Static Random Access Memory, or SRAM, is a vital memory technology for many designs thanks to its fast access time and ability to retain data without memory refresh cycles. However, even though SRAM holds its data while powered on, it will forget this data when powered down as the memory cells use transistors to hold the state. Therefore, SRAM cannot be used to store permanent data such as device configuration, files, or logged data, but instead is used for variables, running programs, and temporary storage.
Recently, Infineon has announced the release of its second-generation SRAM that is non-volatile (i.e. retains its data even when powered down). The new memory devices, STK14C88C and STK14CA8C hold 256kb and 1Mb respectively as parallel memory devices, and are available in 32-pin 300 mil DIL ceramic packages.
These devices conform to MIL-PRF-38535 QML-Q specifications with an operating temperature range of -55°C to 125°C and also conform to Infineon industrial standards. Both versions of the new line of SRAM devices support boot code, logging, and calibration data for systems that need to immediately place program data into RAM on startup.
How does Infineon nvSRAM work?
During operation, the new SRAM devices operate exactly as any SRAM device would; address pins access different storage locations, and the WE, OE, and CS pins allow for reading and writing to and from the SRAM cells. However, the SRAM developed by Infineon is stated as non-volatile meaning it will remember its data even when powered down.
To achieve this, the SRAM devices have a shadow memory that utilises a “Quantum Trap” layer. In essence, the devices have an onboard flash memory storage area that automatically loads and saves the contents of memory when the chip is powered up and down.
Using automatic save and load features is highly beneficial for backup, but such a feature is only practical if it occurs during a sudden loss of power. As such, the new range of Infineon devices provides this feature with the use of a VCAP pin that is connected to an external capacitor. Upon loss of power, the VCAP pin provides enough charge to trigger the auto-save feature of the chip.
The QuantumTrap technology provides storage for at least 20 years, and the memory endurance of the onboard memory is 1 million reads, write, and recall cycles (the SRAM memory cells do not have an endurance limited, only the shadow memory). In applications where this feature is not wanted, the use of software routines will prevent the chip from using the auto store features, and as such the external capacitor can be omitted.
Example of shadow memory in SRAM – Image courtesy Cypress
Potential Applications for nvSRAM
At first glance, such a device could be seen as being useful for storing the state of computing systems each time it powers down. However, the use of Quantum Trapping technology means that an application that frequently powers up and down could result in degradation of the shadow memory (just like with any FLASH memory).
As such, the use of nvSRAM finds itself more suited for always-on devices in extreme applications that must have a high degree of reliability. For example, an industrial controller that must not forget its settings could utilise such memory so that during a blackout, core values such as register states and RAM contents can be preserved and recovered.
Such memory can also be used as a system RAM debugger. A system utilising such a chip could utilise the device to retain the state of the system during a system failure. For example, a microcontroller using the SRAM as external program memory could utilise an error interrupt to disconnect power to the chip, or the system as a whole. Upon this power cycle, the chip would clone the contents of RAM, and then restart. From there, the designer can examine the contents of RAM, and explore why the system failed.
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