Automotive quality RISC-V processor functional design verification solutions

Imperas Software Ltd has announced that NSITEXE, Inc has chosen ImperasDV for advanced RISC-V processor hardware design verification. This expands and extends the usage of the company's simulation technology, models, verification IP and tools by NSITEXE for the next generation of 64bit RISC V-based designs providing vector accelerators for AI automotive applications with verification leading to the level needed to attain ISO 26262 ASIL D.

ImperasDV is the integrated solution for RISC-V processor verification that offers an adaptable framework based on the open standard RVVI that supports the core RTL verification with the Imperas reference model in a 'lock-step-compare' methodology as well as to test suites and other verification IP. It covers the verification tasks for implementations that vary from basic controllers to advanced designs providing vector extensions, privileged mode security protections, multi-hart, and custom extensions. Also, the freedom of the open standard ISA of RISC-V enables advanced processor technology in numerous new application areas with developers investigating techniques such as superscalar, out-of-order execution, multi-threading, heterogeneous multi-core and processor arrays, plus other new and creative approaches for the next generation of domain-specific devices. The solution complements the verification tasks for development teams at the forefront of processor exploration.

"The flexibility of the RISC-V ISA coupled with the performance of vector extensions is an ideal starting point for AI accelerators for automotive applications," said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation. "To address the verification requirement for our next generation of processors, we have developed an optimized verification flow with ImperasDV that our design team set up with detailed configuration options to deliver on their comprehensive verification plans that provides the industry-leading quality our customers expect."

"The open ISA of RISC-V is enabling a new wave of processor design innovation across the spectrum of compute requirements in almost all market segments," said Nobuyuki Ueyama, President of eSOL TRINITY Co., Ltd. "High-quality processor verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV enables the eSOL TRINITY team to support the expert design teams at NSITEXE and other leading adopters of RISC-V in Japan."

"The open standard ISA of RISC-V is enabling a fundamental shift in processor development, with developers able to explore and innovate solutions with optimized solutions for targeted applications," said Simon Davidmann, CEO at Imperas Software Ltd. "The flexibility of RISC-V on the design side has a direct impact on the verification task, and since the value-added features are central to the development, we developed ImperasDV to be adaptable for all implementations to allows our customers and users to verify state-of-the-art designs independently. NSITEXE are pioneers in developing advanced RISC-V vector accelerators for AI, and we are pleased to see the Imperas technology and ImperasDV supporting the quality requirements for automotive applications."