Cadence Design Systems and United Microelectronics Corporation announced that the Cadence digital full flow has been optimised and certified for the UMC 22ULP/ULL process technolog

Design & Manufacture | 16-07-2021

Cadence Design Systems has released the Cadence Tensilica FloatingPoint DSP family, which offers a scalable and configurable solution created specifically for floating-point-centri

Design & Manufacture | 22-06-2021

Cadence Design Systems has launched the Cadence Allegro X Design Platform, the industry’s first engineering platform for system design that unifies schematic, analysis, layout, des

Design & Manufacture | 14-06-2021

Cadence Design Systems has released a straightforward, secure and cost-effective approach to obtaining access to compute resources in the cloud when executing 3D electromagnetic si

Subs & Systems | 04-06-2021

Cadence Design Systems has announced it is expanding its collaboration with Arm to expedite hyperscale computing and 5G communications SoC development using Cadence tools and the n

New Technologies | 04-05-2021

Cadence Design Systems has expanded its Tensilica Vision DSP product family with the launch of two new DSP IP cores for embedded vision and AI. Packing an industry-leading 3.8TOPS,

Subs & Systems | 27-04-2021

Cadence Design Systems has optimised the Cadence digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm. Within the collaboration, designers can emp

New Technologies | 13-04-2021

Cadence Design Systems has extended its system analysis product line by introducing the Cadence Clarity 3D Transient Solver, a system-level simulation solution that solves EMI syst

New Technologies | 20-10-2020

Cadence Design Systems announced the Cadence IP for GDDR6 is silicon-proven on TSMC’s N6, immediately obtainable on both N6 and N7 and forthcoming for TSMC N5 process technologies.

Semiconductors | 15-10-2020

Cadence Design Systems offers its silicon-proven Cadence UltraLink D2D PHY IP on the TSMC N7 process. Test silicon on the process with full silicon characterisation data is now off

Subs & Systems | 02-09-2020

Cadence Design Systems has launched the Cadence Xcelium Logic Simulator, enhanced with machine learning (ML) technology, called Xcelium ML, to further verification throughput. Usin

Test & Measurement | 14-08-2020

Cadence Design Systems has announced that software for Cadence Tensilica HiFi DSPs has been optimised to efficiently execute TensorFlow Lite for Microcontrollers, part of the Tenso

Subs & Systems | 18-03-2020

Cadence Design Systems has announced the availability of the new Cadence CloudBurst Platform for hybrid cloud environments, offering clients with fast and easy access to pre-instal

New Technologies | 03-04-2019

Cadence Design Systems has unveiled what is claimed to be the industry’s first silicon-proven, long-reach 112G SerDes IP in 7nm. The Cadence 7nm 112G PAM-4 SerDes IP produces indus

New Technologies | 24-10-2018